A MOS static RAM is usually provided with a sense amplifier together with a memory array composed of a plurality of static memory cells which are arranged in matrix form, a plurality of word lines with which the selection terminals of the memory cells arranged in the same rows are connected in common, and a plurality of data lines with which the data terminals of the memory cells arranged in the same columns are connected in common. A data signal of comparatively low level delivered from a selected memory cell is amplified by the sense amplifier.
In a circuit arrangement in which a data line to be selected among the plurality of data lines in the memory array is coupled to a common data lines through a column switch circuit, the sense amplifier has its input terminal connected to the common data line. In this case, the output terminal of a writing circuit is also connected to the common data line. Accordingly, in the operation of reading out data, the data signal read out from the memory cell which has been selected by the word line and the column switch circuit is supplied to the sense amplifier through a common word line, while in the operation of writing data, a data signal delivered from the writing circuit is supplied to the selected memory cell through the common word line. In the operation of reading out data, the read-out operation speed is limited by the period of time in which the potentials of the data line and the common data line are brought to predetermined values in accordance with the data signal delivered from the memory cell, and the operating characteristics of the sense amplifier.
The sense amplifier constructed of insulated-gate field effect transistors (hereinbelow, termed "MOSFETs"), especially the sense amplifier of differential circuit form, has its sensitivity affected by the varying range of an input signal to be impressed on the input terminal thereof. When the varying range of the input signal becomes larger or smaller than a desirable varying range, the sensitivity of the sense amplifier decreases.
To increase the data read-out operation speed, the potential of the common data line before the initiation of data read-out can be preset to a desirable level by arranging a MOSFET between, for example, a power source terminal and the common data line, the MOSFET causing a proper voltage drop of a magnitude equal to or greater than the threshold voltage thereof. Similarly, the potential of the data line can be preset to a desirable level by arranging an appropriate MOSFET between the power source terminal and the data line. In this case, since the potentials of the common data line and the data line are preset to the prescribed values in a period such as a chip non-selection period, the period of time in which these potentials are brought to the predetermined values according to the data signal delivered from the memory cell becomes comparatively short. In addition, since the highest potentials of the common data line and the data line are limited by the MOSFETs, the sensitivity of the sense amplifier is enhanced. It is consequently possible to make the data read-out speed comparatively high. However, the MOSFETs for applying the bias voltages as described above give rise to non-negligible leakage currents or tailing currents
Where the chip non-selection period is comparatively long, the potentials of the common data line and the data line are increased approximately to the potential of the power source terminal by the leakage currents or tailing currents. The magnitudes of these leakage or tailing currents of the MOSFETs increase with a rise in temperature. Therefore, when the temperature rises, the potentials of the common data line and the data line are responsively increased to undesirable levels in a comparatively short time. In response to the excessive potentials of the common data line and the data line, the sensitivity of the sense amplifier is decreased, so that the data read-out speed is limited.
For an arrangement in which the sense amplifier in the differential circuit form is controlled by a chip selection signal, when the potential of the common data line is abnormally high as described above, the output voltage of this sense amplifier is decreased considerably irrespective of the level of the data read out from the memory cell, immediately after this amplifier has been brought into its operative state by the chip selection signal. The output voltage of the sense amplifier is thereafter made equal to a level corresponding to the data level delivered from the memory cell. Accordingly, the data read-out speed is also limited by such output a characteristic of the sense amplifier.